The present disclosure relates generally to integrated circuit design, and more particularly, to a structure for a capacitor component in a circuit for protecting the core circuitry of an integrated circuit from damage that may be caused by electrostatic discharge (ESD).
A gate oxide of any metal-oxide-semiconductor (MOS) transistor, in an integrated circuit, is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than the supply voltage. It is understood that a regular voltage is 5.0, 3.3, 3.1 volts, or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. So, it is of critical importance to discharge any static electric charge, as it builds up, before it accumulates to a damaging voltage.
ESD is only a concern to an IC before it is installed into a larger circuit assembly, such as a printed circuit board (PCB), and before the PCB is connected to operating power. This susceptible period includes production, storage, transport, handling, and installation. After the power is supplied, the power supplies and the structures can easily absorb or dissipate electrostatic charges.
ESD protective circuitry is typically added to ICs at the bond pads. The pads are the connections to the IC, to outside circuitry, for all electric power supplies, electric grounds, and electronic signals. Such added circuitry must allow normal operation of the IC. That means that the protective circuitry is effectively isolated from the normally operating core circuitry and it blocks current flow through itself to ground, or any other circuit or pad. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuitry of the IC are supplied to other pads for delivery to external circuits and devices. In an isolated, unconnected IC, all pads are considered to be electrically floating, or of indeterminant voltage. In most cases, that means that the pads are at ground, or zero, voltage.
ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply at a randomly selected pad, the protection circuitry acts differently then it does when the IC is operating normally. When an ESD event occurs, the protection circuitry must quickly become conductive so that the electrostatic charge is conducted to VSS or ground, and is, thusly, dissipated before damaging voltage builds up.
ESD protection circuitry, therefore, has two states. In a normally operating IC, ESD protection circuitry appears invisible to the IC by blocking current through itself and, thusly, having no effect on the IC. In an isolated, unconnected IC, ESD protection circuitry serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS or ground before a damaging voltage can build up.
In a typical ESD protection circuit such as a capacitor-couple type or a gate driven type, an RC circuit module comprised of a resistor and a capacitor (RC), controls an inverter or a gate of a transistor, which further switches a large N-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) which conducts the ESD charge to ground. The capacitor needs to be large enough that, in combination with the resistor, it can provide a large RC time constant. During the beginning of the delay provided by the RC time constant, the voltage on the capacitor builds up slowly from zero to the switching threshold of the inverter. That delay, until the inverter switches, must be long enough for the dissipation of the ESD charge. The value of the capacitor and the quality of the capacitor are critical.
As feature sizes of transistors in ICs shrink to sub-micron sizes, the gate oxide thickness also becomes thinner. The same oxides are conveniently used as the dielectric in the construction of the capacitor in an ESD protection circuit. If the dielectric oxide of the capacitor is too thin, then the oxide is electrically leaky, then the current will also be conducted by the resistor, and the voltage on the capacitor will rise toward the threshold voltage. The risen voltage can potentially cause the large NMOSFET to have a large leakage current flowing from VCC and VSS. In such a case, too much power would be consumed and the circuit is not acceptable.
If a thick oxide is used for the capacitor, since the capacitance per unit area is much smaller than a thin oxide capacitor, a larger area is needed for obtaining the same capacitance. Further, the normal thick oxide capacitors have a non-linear capacitance performance.
What is needed is an oxide to be used as the dielectric in the capacitor that provides reasonably large capacitance per unit area and does not allow electrical leakage.